Conventionally, a wiring substrate in which electronic components are incorporated is known. Japanese Laid-Open Patent Publication No. 2014-49558 describes an example of such wiring substrates. The electronic component is arranged in a cavity that is formed in a core substrate of the wiring substrate. The wiring substrate is manufactured by the following process. Firstly, a temporary tape is applied to one surface side of the core substrate to cover a cavity formed in the core substrate and having a larger size than the electronic component. After the electronic component is arranged in the cavity, the cavity is filled with an insulating resin. Then, the temporary tape is removed and an insulating resin is laminated on the surface of the core substrate from which the temporary tape is removed. In this manner, the structure illustrated in FIG. 11A is obtained. In this structure, the electronic component 203 is arranged in the cavity 202 of the core substrate 201. The insulating resin 204 that covers the electronic component 203 is formed on the upper and lower surfaces of the core substrate 201. The cavity 202 is filled with the insulating resin 204. At this time, the insulating resin 204 is in a semi-cured state. Then, as illustrated in FIG. 11B, the insulating resin 204 in the semi-cured state is thermally cured and hardened under a temperature atmosphere of about 150° C. to 180° C. In the thermal cure processing, the core substrate 201 and the electronic component 203 are expanded by the high temperature (refer to arrows in FIG. 11B). The position of each of the components is fixed by hardening of the insulating resin 204. Subsequently, in the step illustrated in FIG. 11C, the structure illustrated in FIG. 11B is cooled. Then, a given number of insulating layers and a given number of wiring layers are stacked on each of the upper and lower surfaces of the insulating resin 204.
The electronic component 203 has a lower coefficient of thermal expansion (CTE) than the core substrate 201. In this case, the contraction of the core substrate 201 becomes larger than that of the electronic component 203 during the cooling. This applies compressive stress to the electronic component 203 (refer to arrows in FIG. 11C). When the compressive stress applied to the electronic component 203 becomes large, the peripheral portion of the electronic component 203 is deformed by the compressive stress. Consequently, as illustrated in FIG. 11D, the electronic component 203 is protruded from one surface side. In such a case, it is difficult to form wirings on the insulating resin 204.
If a gap between the electronic component 203 and the walls of the cavity 202 is widely ensured, the insulating resin 204 filled in the gap may limit the compressive stress applied to the electronic component 203 during the cooling. However, when the volume of the cavity 202 is large, the cavity 202 may not be sufficiently filled with the insulating resin 204. This may form dips in the insulating resin 204 covering the top of the cavity 202. Such dips adversely affect the formation of the wiring layers on the insulating resin 204.